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| this is information on a product in full production. may 2012 doc id 023240 rev 1 1/51 51 l6759d 3+1 dual controller for vr12 with pmbus datasheet ? production data features vr12 compliant with 25 mhz svid bus rev1.5 ? serialvid with programmable imax, tmax, vboot, address second generation ltb technology? flexible driver/drmos support jmode support fully configurable through pmbus dual controller: ? 3-phase for vddq ? 1-phase for vtt single ntc design for tm, ll and imon thermal compensation vfde and gdc - gate drive control for efficiency optimization dpm - dynamic phase management dual remote sense 0.5% output voltage accuracy full-differential current sense across dcr avp - adaptive voltage positioning dual independent adjustable oscillator dual current monitor pre-biased output management average and per-phase oc protection ov, uv and fb disconnection protection dual vr_rdy vfqfpn48 6x6 mm package application ddr3 memory supply for vr12 servers description the l6759d is a dual controller designed to power intel?s vr12 processor memories: all required parameters are programmable through dedicated pin-strapping and pmbus interface. the device features 3-phase programmable operation for the multi-phase section and a single- phase with independent control loops. single- phase (vtt) reference is always tracking multi- phases (vddq) scaled by a factor of 2. the l6759d supports power state transitions featuring vfde, programmable dpm and gdc maintaining the best efficiency over all loading conditions without compromising transient response. the device assures fast and independent protection against load overcurrent, under/overvoltage and feedback disconnections. the device is available in a vfqfpn48 6x6 mm package. table 1. device summary order code package packing l6759d vfqfpn48 6x6mm tr ay L6759DTR tape and reel vfqfpn48 - 6x6mm www.st.com
contents l6759d 2/51 doc id 023240 rev 1 contents 1 typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 5 1.1 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 pin description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 device configuration and pin-strapping tables . . . . . . . . . . . . . . . . . . 17 4.1 jmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 programming hiz level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 output voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 multi-phase section - phase # programming . . . . . . . . . . . . . . . . . . . . . . 22 6.2 multi-phase section - current reading and current sharing loop . . . . . . . . 22 6.3 multi-phase section - defining load-line . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.4 multi-phase section - imon information . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.5 single-phase section - disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.6 single-phase section - current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.7 single-phase section - defining load-line . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.8 dynamic vid transition support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.9 dvid optimization: ref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 output voltage monitoring and protection . . . . . . . . . . . . . . . . . . . . . . 28 7.1 overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.2 overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 l6759d contents doc id 023240 rev 1 3/51 7.2.1 multi-phase section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2.2 overcurrent and power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2.3 single-phase section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 single ntc thermal monitor and compensation . . . . . . . . . . . . . . . . . 32 8.1 thermal monitor and vr_hot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.2 thermal compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.3 tm and tcomp design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9 efficiency optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.1 dynamic phase management (dpm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.2 variable frequency diode emulation (vfde) . . . . . . . . . . . . . . . . . . . . . . 35 9.3 gate drive control (gdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.1 lsless startup and pre-bias output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11 system control loop compensati on . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.1 compensation network guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11.2 ltb technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12 pmbus support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12.1 enabling the device through pmbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.2 controlling vout through pmbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.3 input voltage monitoring (read_vin) . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12.4 duty cycle monitoring (read_duty) . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12.5 output voltage monitoring (read_vout) . . . . . . . . . . . . . . . . . . . . . . . . 46 12.6 output current monitoring (read_iout) . . . . . . . . . . . . . . . . . . . . . . . . 46 12.7 temperature monitoring (read_temperature) . . . . . . . . . . . . . . . . . 46 12.8 overvoltage threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 list of tables l6759d 4/51 doc id 023240 rev 1 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 6. pin-strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 7. pmbus address definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 8. l6759d protection at a glance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 9. multi-phase section oc scaling and power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 10. efficiency optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 11. supported commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 12. ov threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 13. vfqfpn48 (6x6 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 14. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 l6759d list of figures doc id 023240 rev 1 5/51 list of figures figure 1. typical 3-phase application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. typical 2-phase application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. jmode: voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. device initialization: default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7. device initialization: alternative sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 8. voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 9. current reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 10. dvid optimization circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 11. thermal monitor connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 12. output current vs. switching frequency in psk mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 13. efficiency performances with and without enhancements (dpm, gdc) . . . . . . . . . . . . . . 36 figure 14. rosc vs. f sw per phase (r osc to gnd - left; r osc to 3.3v - right) . . . . . . . . . . . . . . . . 38 figure 15. lsless startup: enabled (left) and disabled (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 16. equivalent control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 17. control loop bode diagram and fine tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 18. device initialization: pmbus controlling vout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 figure 19. vfqfpn48 (6x6 mm) package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 typical application circuit and block diagram l6759d 6/51 doc id 023240 rev 1 1 typical application circuit and block diagram 1.1 application circuit figure 1. typical 3-phase application circuit h s 1 l s 1 l1 c hf c dec r c boot ugate pha s e lgate pwm vcc l6747 en +12v r g h s 2 l s 2 l2 c hf r c boot ugate pha s e lgate vcc l6747 en +12v r g h s3 l s3 l 3 c hf r c boot ugate pha s e lgate vcc l6747 en +12v r g s h s s l s s l c hf boot ugate pha s e lgate pwm vcc l6747 en +12v r g s pwm s c s p s c s n c s3 n c s3 p pwm 3 c s 2n c s 2p pwm2 c s 1n c s 1p pwm1 vr12 load uncore core vr12 svid bu s c out c mlcc c s out c s mlcc gnd pwm gnd pwm gnd gnd c dec c dec c dec vr12 svid bu s s vclk alert# s vdata c f r f c i r i r fb c p rgnd v s en fb comp c ref r ref ref c s f r s f c s i r s i r s fb c s p s rgnd s v s en s fb s comp c ltb r ltb ltb endrv imax +12v vdrv s drp / addr o s c s o s c +5v vcc5 gdc gnd (pad) vrrdy s vrrdy vr_rdy s vr_rdy vr_hot vr_hot en en r imon imon +5v r ilim ilim tm vcc5 ntc (nth s 0 8 05n02n6 8 01) st l6759d s t l6759d ( 3 +1) reference s chem a tic s fbr c ilim fbr c imon +5v s mal# s mdata s mclock smbu s tcomp pha s e vin +12v (vin s en s e) to pha s e1 (ntc option a l) l6759d typical application circuit and block diagram doc id 023240 rev 1 7/51 figure 2. typical 2-phase application circuit h s 1 l s 1 l1 c hf c dec r c boot ugate pha s e lgate pwm vcc l6747 en +12v r g h s 2 l s 2 l2 c hf r c boot ugate pha s e lgate vcc l6747 en +12v r g s h s s l s s l c hf boot ugate pha s e lgate pwm vcc l6747 en +12v r g s pwm s c s p s c s n c s3 n c s3 p pwm 3 c s 2n c s 2p pwm2 c s 1n c s 1p pwm1 vr12 load uncore core vr12 svid bu s c out c mlcc c s out c s mlcc gnd pwm gnd gnd c dec c dec vr12 svid bu s s vclk alert# s vdata c f r f c i r i r fb c p rgnd v s en fb comp c ref r ref ref c s f r s f c s i r s i r s fb c s p s rgnd s v s en s fb s comp c ltb r ltb ltb endrv imax +12v vdrv s drp / addr o s c s o s c +5v vcc5 gdc gnd (pad) vrrdy s vrrdy vr_rdy s vr_rdy vr_hot vr_hot en en r imon imon +5v r ilim ilim tm vcc5 ntc (nth s 0 8 05n02n6 8 01) st l6759d s t l6759d (2+1) reference s chem a tic s fbr c ilim fbr c imon +5v s mal# s mdata s mclock smbu s tcomp pha s e vin +12v (vin s en s e) to pha s e1 (ntc option a l) to vcc5 r g typical application circuit and block diagram l6759d 8/51 doc id 023240 rev 1 1.2 block diagram figure 3. block diagram pwm2 pwm1 pwm1 pwm2 pwm 3 ltb technology mod u l a tor & fre qu ency limiter r a mp & clock gener a tor with vfde dpm control s s s differenti a l c u rrent s en s e c u rrent b a l a nce & pe a k c u rr limit therm a l compen sa tion a nd g a in a dj us t c s 1p c s 1n c s 2p c s 2n c s3 p c s3 n lt b error amplifier tm tcomp vr_hot i lim i droop voc_tot vr12 b us m a n a ger & pin s tr a pping m a n a ger fb ref comp s v data alert# s vclk ilim d ua l dac & ref gener a tor vr12 regi s ter s imax addr rgnd fbr ov +175mv m u ltiph as e f au lt m a n a ger oc s ref therm a l s en s or a nd monitor tempzone tempzone imon s imon ch a n # n ltb technology mod u l a tor & fre qu ency limiter r a mp & clock gener a tor withvfde s o s c s pwm / s en s pwm error amplifier i s droop s fb s comp s ov +175mv s ingleph as e f au lt m a n a ger vr_rdy flt flt to s ingleph as e flt m a n a ger to m u ltiph as e flt m a n a ge s vr_rdy s flt s flt differenti a l c u rrent s en s e s c s p s c s n s t a rt- u p logic & gdc control vdrv vcc5 gdc en endrv s _en en s _en gnd (pad) o s c v s en i ref i ref pmb us (tm) decodific a tion engine & control logic s m data s mal# s mclk vin pha s e ch a n # v s en, s v s en vid, s vid dpm dpm dpm l6759d i mon imon v s en remote buffer ref ref ref s rgnd s fbr s v s en s ref pwm 3 l6759d pin description and connection diagrams doc id 023240 rev 1 9/51 2 pin description and connection diagrams figure 4. pin connection (top view) 2.1 pin description 4 8 47 46 45 44 4 3 42 41 40 3 9 38 3 7 1 3 14 15 16 17 1 8 19 20 21 22 2 3 24 3 6 3 5 3 4 33 3 2 3 1 3 0292 8 27 26 25 12 3 4567 8 9101112 tm s pwm vr_hot tcomp s c s p ilim s rgnd s fbr s v s en s fb s comp s c s n endrv s vr_rdy imon ref rgnd ltb fbr v s en fb comp vdrv gdc vcc5 s v data alert# s vclk en vin o s c ( s )drp/addr s mclock s malert# s m data imax/ s imax pwm 3 pwm2 pwm1 pha s e vr_rdy c s3 p c s3 n c s 2n c s 2p c s 1p c s 1n s o s c l6759d table 2. pin description pin# name function 1 to 3 pwm3 to pwm1 multi-phase section pwm outputs. connect to multi-phase external drivers pwm input. these pins are also used to configure hiz levels for compatibility with drivers and drmos. during normal operations the device is able to manage the hiz status by setting and holding the pwmx pin to a pre-defined fixed voltage. connect pwm3 to 5 v through 1 kw resistor to program 2-phase opera- tion. 4 phase connect through resistor divider to channel1 multi-phase switching node. 5 vr_rdy vr ready. open drain output set free after ss has finished in multi- phase and pulled low when triggering any protection on the multi-phase section. pull up to a voltage lower than 3.3 v (typ.), if not used it can be left floating. 6cs3p channel 3 current sense positive input. connect through an r-c filter to the phase-side of the channel 3 inductor. when working at 2-phase, short to the regulated voltage. 7cs3n channel 3 current sense negative input. connect through an rg resistor to the output-side of the channel inductor. when working at 2-phase, still connect through rg to cs3p and then to the regulated voltage. fil- ter the output-side of rg with 100 nf (typ.) to gnd. pin description and connection diagrams l6759d 10/51 doc id 023240 rev 1 8cs2n multi-phase section channel 2 current sense negative input. connect through an rg resistor to the output-side of the channel inductor. filter the output-side of rg with 100 nf (typ.) to gnd. 9cs2p channel 2 current sense positive input. connect through an r-c filter to the phase-side of the channel 2 inductor. 10 cs1p channel 1 current sense positive input. connect through an r-c filter to the phase-side of the channel 1 inductor. 11 cs1n channel 1 current sense negative input. connect through an rg resistor to the output-side of the channel inductor. filter the output-side of rg with 100 nf (typ.) to gnd. 12 sosc single-phase section oscillator pin. it allows the programming of the switching frequency f ssw for the sin- gle-phase section. the pin is internally set to 1.02 v, frequency for sin- gle-phase is programmed according to the resistor connected to gnd or vcc with a gain of 11.5 khz/a. leaving the pin floating programs a switching frequency of 230 khz. see s ection 10 for details. 13 tm multi-phase section thermal monitor sensor. connect with the proper network embedding ntc to the multi-phase power section. the ic senses the power section temperature and uses the information to define the vr_hot signal and temperature zone reg- ister. by programming proper tcomp gain, the ic also implements load-line thermal compensation for the multi-phase section. in jmode, the pin disables the single-phase section if shorted to gnd. pull up to vcc5 with 1 k ? to disable the thermal sensor. see s ection 6 for details. 14 spwm / sen single-phase section pwm output. connect to single-phase external driver pwm input. during normal operations the device is able to manage hiz status by setting and hold- ing the spwm pin to a fixed voltage defined by pwmx strapping. connect to vcc5 with 1 k ? to disable the single-phase section. 15 vr_hot voltage regulator hot. open drain output, this is an alarm signal asserted by the controller when the temperature sensed through the tm pin exceeds tmax (active low). see s ection 6 for details. 16 tcomp multi-phase section thermal monitor sensor gain. connect the proper resistor divider between vcc5 and gnd to define the gain to apply to the signal sensed by tm to implement thermal com- pensation for the multi-phase section. short to gnd to disable tempera- ture compensation (but not thermal monitor). see s ection 6 for details. 17 scsp single-phase section single-phase section current sense positive input. connect through an r-c filter to the phase-side of the channel 1 inductor. 18 scsn single-phase section current sense negative input. connect through an rg resistor to the output-side of the channel inductor. filter the output- side of rg with 100 nf (typ.) to gnd. table 2. pin description (continued) pin# name function l6759d pin description and connection diagrams doc id 023240 rev 1 11/51 19 i lim single-phase section multi-phase section current limit. a current proportional to the multi-phase load current is sourced from this pin. connect through a resistor r lim to gnd. when the pin voltage reaches 2.5 v, the overcurrent protection is set and the ic latches. filter through c lim to gnd to delay oc intervention. 20 srgnd remote buffer ground sense. connect to the negative side of the single-phase load to perform remote sense. 21 sfbr remote buffer positive sense. connect to the positive side of the single-phase load to perform remote sense. 22 svsen remote buffer output. output voltage monitor, manages ov and uv protection. connect with a resistor r sfb // (r si - c si ) to sfb. 23 sfb error amplifier inverting input. connect with a resistor r sfb // (r si - c si ) to svsen and with an (r sf - c sf )// c sh to scomp. 24 scomp error amplifier output. connect with an (r sf - c sf )// c sh to sfb. the device cannot be dis- abled by pulling low this pin. 25 imax pin-strapping connect a resistor divider to gnd/vcc5 in order to define the imax register. jmode and boot voltage can be controlled through this pin. see ta bl e 6 and s ection 6 for details. 26 smdata pmbus pmbus data. 27 smal# pmbus alert. 28 smclock pmbus clock. 29 addr pin-strapping connect a resistor divider to gnd/vcc5 in order to define the ic address, to define the gdc and dpm thresholds and to control the droop function on multi-phase. see ta bl e 6 and s ection 6 for details. 30 osc multi-phase section oscillator pin. it allows the programming of the switching frequency f sw for the multi- phase section. the pin is internally set to 1.02 v, the frequency for multi- phase is programmed according to the resistor connected to gnd or vcc with a gain of 10 khz/a. leaving the pin floating programs a switching frequency of 200 khz per phase. the effective frequency observable on the load results being multiplied by the number of active phases n. see s ection 10 for details. 31 vin input voltage monitor. connect to input voltage monitor point through a divider r up / r down to perform vin sense through pmbus (r up . = 118.5 k ?; r down = 10 k ? typ.). see s ection 12.3 for details. table 2. pin description (continued) pin# name function pin description and connection diagrams l6759d 12/51 doc id 023240 rev 1 32 en vtt level sensitive enable pin (3.3 v compatible). pull low to disable the device, pull up above the turn-on threshold to enable the controller. 33 svclk svi bus serial clock. 34 alert# alert. 35 svdata serial data. 36 vcc5 main ic power supply. operative voltage is 5 v 5%. filter with 1 f mlcc to gnd (typ.). 37 gdc gate drive control pin. used for efficiency optimization, see s ection 9 for details. if not used, it can be left floating. always filter with 1 f mlcc to gnd. 38 vdrv driving voltage for external drivers. connect to the selected voltage rail to drive the external mosfet when in maximum power conditions. ic switches gdc voltage between vdrv and vcc5 to implement efficiency optimization according to selected strategies. 39 comp / addr multi-phase section error amplifier output. connect with an (r f - c f )// c p to fb. the device cannot be disabled by pulling low this pin. connect r comp to gnd to extend pmbus addressing range (see ta bl e 6 ). 40 fb error amplifier inverting input. connect with a resistor r fb // (r i - c i ) to vsen and with an (r f - c f )// c p to comp. 41 vsen output voltage monitor, manages ov and uv protection. connect to the positive side of the load to perform remote sense. 42 fbr remote buffer positive sense. connect to the positive side of the multi-phase load to perform remote sense. 43 ltb load transient boost technology ? input pin. see s ection 11.2 for details. 44 rgnd remote ground sense. connect to the negative side of the multi-phase load to perform remote sense. 45 ref the reference used for the multi-phase section regulation is available on this pin with -125 mv offset. connect through an r ref -c ref to gnd to optimize dvid transitions. connect through r os resistor to fb pin to implement small positive offset to the regulation. 46 imon current monitor output. a current proportional to the multi-phase load current is sourced from this pin. connect through a resistor r mon to gnd. the information available on this pin is used for the current reporting and dpm. the pin can be filtered through c imon to gnd. table 2. pin description (continued) pin# name function l6759d pin description and connection diagrams doc id 023240 rev 1 13/51 2.2 thermal data table 3. thermal data 47 svr_rdy single-phase section vr ready. open drain output set free after ss has finished in single-phase section and pulled low when triggering any protection for the single-phase sec- tion.pull up to a voltage lower than 3.3 v (typ.), if not used it can be left floating. 48 endrv multi-phase section enable driver. cmos output driven high when the ic commands the drivers. used in conjunction with the hiz window on the pwmx pins to optimize the multi-phase section overall efficiency. connect directly to external driver enable pin. pa d g n d gnd connection. all internal references and logic are referenced to this pin. filter to vcc with proper mlcc capacitor and connect to the pcb gnd plane. table 2. pin description (continued) pin# name function symbol parameter value unit r thja thermal resistance junction to ambient (device soldered on 2s2p pc board) 40 c/w r thjc thermal resistance junction to case 1 c/w t max maximum junction temperature 150 c t stg storage temperature range -40 to 150 c t j junction temperature range 0 to 125 c electrical specifications l6759d 14/51 doc id 023240 rev 1 3 electrical specifications 3.1 absolute maximum ratings 3.2 electrical characteristics v cc5 = 5 v 5%, t j = 0 c to 70 c unless otherwise specified. table 4. absolute maximum ratings symbol parameter value unit vdrv, gdc to gnd -0.3 to 14 v vcc5, tm, stm, spwm, pwmx, sendrv, endrv, scomp, comp, smdata, smal#, smclk to gnd -0.3 to 7 v all other pins to gnd -0.3 to 3.6 v table 5. electrical characteristics symbol parameter test conditions min. typ. max. unit supply current and power-on i vcc5 vcc5 supply current en = high 28 ma en = low 22 ma uvlo vcc5 vcc5 turn-on vcc5 rising 4.1 v vcc5 turn-off vcc5 falling 3 v uvlo vdrv vdrv turn-on vdrv rising 6 v vdrv turn-off vdrv falling 3 4.1 v uvlo vin vin turn-on vin rising, r up . = 118.5 k ?; r down = 10 k ? 6v vin turn-off vin falling, r up . = 118.5 k ?; r down = 10 k ? 34.1v oscillator, soft-start and enable f sw main oscillator accuracy osc = open 170 200 230 khz oscillator adjustability r osc = 47 k ? to gnd 378 420 462 khz f ssw main oscillator accuracy sosc = open 195 230 265 khz oscillator adjustability r sosc = 47 k ? to gnd 432 480 528 khz ? v osc pwm ramp amplitude (1) 1.5 v fault voltage at pin osc, ssosc latch active for related section 3 v l6759d electrical specifications doc id 023240 rev 1 15/51 soft- start ss time vboot > 0, from pin-strapping; multi- phase section 2.5 mv/ s vboot > 0, from pin-strapping; single-phase section 1.25 mv/ s vboot > 0, from pin-strapping; single-phase section, jmode on 2.5 mv/ s en tu r n - o n v en rising 0.6 v tu r n - o f f v en falling 0.4 v leakage current 1 a svi serial bus svclck, svdata input high 0.65 v input low 0.45 v svdata, alert# voltage low (ack) i sink = -5 ma 50 mv pmbus smdata, smclk input high 1.75 v input low 1.45 v smal# voltage low i sink = -4 ma 13 ? reference and dac k vid v out accuracy (mphase) fbr to v core ; rgnd to gnd core vid>1.000 v -0.5 0.5 % k svid v out accuracy (sphase) jmode=off; v uncore /v core sfbr to v uncore ; srgnd to gnd uncore ; vid>1.000 v 0.49 0.51 jmode=on; sfbr to v uncore ; srgnd to gnd uncore ; -5 5 mv ? droop ll accuracy (mphase) 0 to full load i infox = 0 a; n=3; r g =866 ? -2.25 1.75 a i infox = 20 a; n=3; r g =866 ? -2.5 2.5 a k imon imon accuracy (mphase) i infox = 0; n=3; r g =866 ? 00.75 a i infox = 20 a; n=3; r g =866 ? -1 1 a a 0 ea dc gain (1) 100 db sr slew-rate (1) comp to sgnd = 10 pf 20 v/ s dvid slew-rate fast multi-phase section 10 mv/ s slew-rate slow 2.5 mv/ s dvid slew-rate fast single-phase section 5mv/ s slew-rate slow 1.25 mv/ s table 5. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit electrical specifications l6759d 16/51 doc id 023240 rev 1 imon adc getreg(15h) v(imon) = 0.992 v cc hex accuracy c0 cf hex pwm outputs and endrv pwmx, spwm output high i = 1 ma 5 v output low i = -1 ma 0.2 v i pwm1 test current sourced from pin, en=0 10 a i pwm2 sourced from pin, en=0 0 a i pwm3, spwm sourced from pin, en=0 -10 a endrv voltage low i endrv = -4 ma 0.4 v protection (both sections) ovp overvoltage protection vsen rising; wrt ref. 100 200 mv uvp undervoltage protection vsen falling; wrt ref; ref > 500 mv -525 -375 mv fbr disc fb disconnection v cs- rising, above vsen/svsen 650 700 750 mv fbg disc fbg disconnection fbr rising wrt vid 950 1000 1050 mv vr_rdy, svr_rdy voltage low i sink = -4 ma 0.4 v v oc_tot oc threshold v ilim rising, to gnd 2.45 2.5 2.55 v i oc_th constant current (1) mphase only 35 a vr_hot voltage low i sink = -4 ma 13 ? gate drive control gdc max. current (1) any ps 200 ma impedance ps00h (gdc = vdrv) 6 ? > ps00h (gdc = vcc5) 6 ? 1. guaranteed by design, not subject to test. table 5. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit l6759d device configuration and pin-strapping tables doc id 023240 rev 1 17/51 4 device configuration and pin-strapping tables the l6759d is fully compliant with intel ? vr12/imvp7 svid protocol rev1.5, document # 456098. to guarantee proper device and cpu operations, refer to this document for bus design and layout guidelines. different platforms may require different pull-up impedance on the svi bus. impedance matching and spacing between svdata, svclk, and alert# must be followed. 4.1 jmode when enabled, single-phase is an independent regulator with 0.75 v fixed reference (load- line disabled - tm can be used as enable for the single-phase). output voltage higher than the internal reference may be achieved by adding a proper resistor divider (ra, rb - see fig u re 5 ). to maintain precision in output voltage regulation, it is recommended to provide both sfbr and srgnd with the same divider. equation 1 figure 5. jmode: voltage positioning v out 0.750v ra rb + rb ----------------------- ? = 0.750v sfb scomp svsen sfbr r f c f r fb to vout (remote sense) protection monitor srgnd r a r a r b r b device configuration and pin-strapping tables l6759d 18/51 doc id 023240 rev 1 4.2 programming hiz level the l6759d is able to manage different levels for hiz on pwmx guaranteeing flexibility in driving different external drivers as well as drmos ics. once vcc5, vdrv, and vin voltages are above the respective uvlo (undervoltage lockout) thresholds (see fig u re 6 ), the device uses pwm1 and pwm2 to detect the driver/drmos connected in order to program the suitable hiz level of pwmx signals. during regulation, the hiz level is used to force the external mosfets into high impedance state. pwm1 sources a constant 10 a current, if its voltage results higher than 2.8 v, the hiz level used during the regulation is 1.4 v, if lower, pwm2 information is used. pwm2 is kept in hiz, if its voltage results higher than 2 v, the hiz level used during the regulation is 2 v, if lower, 1.6 v. an external resistor divider can be placed on pwm1 and pwm2 to force the detection of the correct hiz level. they must be designed considering the external driver/drmos selected and the hiz level requested. table 6. pin-strapping (1) rdown [k ? ] rup [k ? ] imax addr imax [a] (2) jmode vboot svi addr (3) vfde dpm12 dpm23 droop core 10 1.5 on 1.500 v 0100b off 12 a 24 a on 10 2.7 1.350 v off 22 6.8 off 1.500 v 10 a 20 a on 10 3.6 1.350 v off 27 11 on 1.500 v 8 a 18 a on 12 5.6 1.350 v off 82 43 off 1.500 v off off on 13 7.5 1.350 v off 56 36 on 1.500 v on 12 a 24 a on 18 13 1.350 v off 15 12 off 1.500 v 10 a 20 a on 18 16 1.350 v off 15 14.7 on 1.500 v 8 a 18 a on 10 11 1.350 v off 18 22 off 1.500 v off off on 56 75 1.350 v off n 25 56 + ? n 25 48 + ? n 25 40 + ? n 25 32 + ? l6759d device configuration and pin-strapping tables doc id 023240 rev 1 19/51 10 15 on 1.500 v 0010b off 12 a 24 a on 12 20 1.350 v off 12 22.6 off 1.500 v 10 a 20 a on 39 82 1.350 v off 47 110 on 1.500 v 8 a 18 a on 10 27 1.350 v off 22 68 off 1.500 v off (4) off (5) on 10 36 1.350 v off 18 75 on 1.500 v on 12 a 24 a on 15 75 1.350 v off 10 59 off 1.500 v 10 a 20 a on 10 75 1.350 v off 10 100 on 1.500 v 8 a 18 a on 10 150 1.350 v off 10 220 off 1.500 v off (4) off (5) on 10 open 1.350 v off 1. suggested values, divider needs to be connected between vcc5 pin and gnd. 2. n is the number of phase programmed for the multi-phase section. 3. address for multi-phase. single-phase not accessible. 4. transition between 1phase and 2phase oper ation is set to 12 a but disabled in ps00h (minimum phase number in ps00h is 2). 5. dynamic phase management disabled, ic always working at maximum possible number of phases except when in >ps00h when transitioning between 1phase and 2phase at 12 a. table 6. pin-strapping (1) (continued) rdown [k ? ] rup [k ? ] imax addr imax [a] (2) jmode vboot svi addr (3) vfde dpm12 dpm23 droop core n 25 24 + ? n 25 16 + ? n 25 8 + ? n 25 ? table 7. pmbus address definition svi address (see table 6 ) comp to gnd pmbus address 0100b 4.99 k eeh 14.99 k eah 24.99 k e6h open e2h 0010b 4.99 k ech 14.99 k e8h 24.99 k e4h open e0h device description and operation l6759d 20/51 doc id 023240 rev 1 5 device description and operation the l6759d is a programmable 2/3-phase pwm controller that provides complete control logic and protection to realize a high performance step-down dc-dc voltage regulator optimized for advanced ddr memory power supply. the device features 2 nd generation ltb te c h n o l o gy ? : through a load transient detector, it is able to turn on simultaneously all the phases. this allows the output voltage deviation to be minimized and, in turn, to minimize system costs by providing the fastest response to a load transition. the l6759d implements current reading across the inductor in fully differential mode. a sense resistor in series to the inductor can be also considered to improve reading precision. the current information read corrects the pwm output in order to equalize the average current carried by each phase. the controller supports vr12 specifications featuring 25 mhz svi bus and all the required registers. the platform may program the defaults for these registers through dedicated pin- strapping. a complete set of protection is available: overvoltage, undervoltage, overcurrent (per-phase and total) and feedback disconnection guarantee the load to be safe under all conditions. special power management features like dpm, vfde and gdc modify the phase number, gate driving voltage and switching frequency to optimize the efficiency over the load range. the l6759d is available in vfqfpn48 with a 6x6 mm body package. 5.1 device initialization figure 6. device initialization: default 6 # # 6 $ 2 6 6 ) . 5 6 , / m 3 e c 0 / 2 5 6 , / 5 6 , / u 3 e c % . 3 6 ) " 5 3 0 - " u s 6 $ $ 1 6 4 4 u 3 e c % . 6 4 4 6 2 2 $ 9 3 6 2 2 $ 9 u 3 e c # o m m a n d 2 e j e c t e d # o m m a n d ! # + b u t n o t e x e c u t e d ! - v l6759d device description and operation doc id 023240 rev 1 21/51 figure 7. device initialization: alternative sequence vcc5 vdrv vin uvlo 2m s ec por uvlo uvlo 50 us ec en s vi bu s pmb us vddq / vtt 20 us ec envtt vrrdy / s vrrdy 64 us ec comm a nd rejected comm a nd ack bu t not exec u ted am11 8 06v1 output voltage positioning l6759d 22/51 doc id 023240 rev 1 6 output voltage positioning output voltage positioning is performed by selecting the controller operative-mode for the two sections and by programming the droop function effect (see fig u re 8 ). the controller reads the current delivered by each section by monitoring the voltage drop across the dcr inductors. the current (i droop / i sdroop ) sourced from the fb / sfb pins, directly proportional to the read current, causes the related section output voltage to vary according to the external r fb / r sfb resistor, so implementing the desired load-line effect. the l6759d embeds a dual remote-sense buffer to sense remotely the regulated voltage of each section without any additional external components. in this way, the output voltage programmed is regulated, compensating for board and socket losses. keeping the sense traces parallel and guarded by a power plane results in common mode coupling for any picked-up noise. figure 8. voltage positioning 6.1 multi-phase section - phase # programming the multi-phase section implements a flexible 2 to 3 interleaved-phase converter. to pro- gram the desired number of phases, pull up with a 1 k ? resistor to vcc5 the pwmx signal that is not required to be used. caution: for the disabled phase(s), the current reading pins need to be properly connected to avoid errors in current-sharing and voltage-positioning: csxp needs to be connected to the regulated output voltage while csxn needs to be connected to csxp through the same r g resistor used for the active phases. see fig u re 2 for details on 2-phase connections. 6.2 multi-phase section - current reading and current sharing loop the l6759d embeds a flexible, fully-differential current sense circuitry that is able to read across inductor parasitic resistance or across a sense resistor placed in series to the induc- tor element. the fully-differential current reading rejects noise and allows the placing of the sensing element in different locations without affecting the measurement's accuracy. the ref. from dac fb comp vsen fbr r f c f r fb to vddcore (remote sense) i droop protection monitor rgnd l6759d output voltage positioning doc id 023240 rev 1 23/51 trans-conductance ratio is issued by the external resistor r g placed outside the chip between the csxn pin toward the reading points. the current sense circuit always tracks the current information, the csxp pin is used as a reference keeping the csxn pin to this volt- age. to correctly reproduce the inductor current, an r-c filtering network must be intro- duced in parallel to the sensing element. the current that flows from the csxn pin is then given by the following equation (see fig u re 9 ): equation 2 considering the matching of the time constant between the inductor and the r-c filter applied (time constant mismatches cause the introduction of poles into the current reading network causing instability. in addition, it is also important for the load transient response and to let the system show resistive equivalent output impedance) it results: equation 3 figure 9. current reading the current read through the csxp / csxn pairs is converted into a current i infox propor- tional to the current delivered by each phase and the information about the average current i avg = i infox / n is internally built into the device (n is the number of working phases). the error between the read current i infox and the reference i avg is then converted into a voltage that, with a proper gain, is used to adjust the duty cycle whose dominant value is set by the voltage error amplifier in order to equalize the current carried by each phase. 6.3 multi-phase section - defining load-line the l6759d introduces a dependence of the output voltage on the load current recovering part of the drop due to the output capacitor esr in the load transient. introducing a dependence of the output voltage on the load current, a static error, proportional to the output current, causes the output voltage to vary according to the sensed current. i csxn dcr r g ------------- 1s l dcr ? ? + 1s r c ?? + ------------------------------------------- - i ? phasex ? = l dcr ------------- rc i csxn r l r g ------- - i phasex ? = ? ? i infox == lx csxp csxn dcr x r c r g i phasex inductor dcr current sense i csxn =i infox v out output voltage positioning l6759d 24/51 doc id 023240 rev 1 fig u re 9 shows the current sense circuit used to implement the load-line. the current flowing across the inductor(s) is read through the r-c filter across the csxp and csxn pins. r g programs a trans-conductance gain and generates a current i csx proportional to the current of the phase. the sum of the i csx current, with proper gain eventually adjusted by the pmbus commands, is then sourced by the fb pin (i droop ). r fb gives the final gain to program the desired load-line slope ( fig u re 8 ). time constant matching between the inductor (l / dcr) and the current reading filter (rc) is required to implement a real equivalent output impedance of the system, so voiding over and/or undershoot of the output voltage as a consequence of a load transient. the output voltage characteristic vs. load current is then given by: equation 4 where r ll is the resulting load-line resistance implemented by the multi-phase section. the r fb resistor can be then designed according to the r ll specifications as follows: equation 5 6.4 multi-phase section - imon information the voltage on the imon pin contains the analog information related to the current delivered by the vr and it is digitized for vr12 current reporting. the pin sources a copy of the droop current: equation 6 see s ection 6 for details about current reading. the iout register contains analog-to-digital conversion of the voltage present on the imon pin considering the following relationships: a) where r imon is the resistor connected between imon and gnd. b) v imon =1.24 v corresponds to imax. r imon is designed according to this relationship. note: c u rrent reporting precision may be affected by external layo u t. the internal adc is referenced to the device gnd pin: in order to perform the highest acc u racy in the c u rrent monitor, r imon m u st be ro u ted to the gnd pin with a dedicated net to avoid gnd plane drops affecting the precision of the meas u rement. v out vid r fb i droop ? ? vid r fb dcr r g ------------- i out ?? ? vid r ll i out ? ? == = r fb r ll r g dcr ------------- ? = i imon i droop dcr r g ------------- i out ? == v imon i imon r imon ? = l6759d output voltage positioning doc id 023240 rev 1 25/51 6.5 single-phase section - disable the single-phase section can be disabled by pulling high the spwm pin. the related command is rejected. 6.6 single-phase section - current reading the single-phase section performs the same differential current reading across dcr as the multi-phase section. according to s ection 6.2 , the current that flows from the scsn pin is then given by the following equation (see fig u re 9 ): equation 7 6.7 single-phase section - defining load-line this method introduces a dependence of the output voltage on the load current recovering part of the drop due to the output capacitor esr in the load transient. introducing a depen- dence of the output voltage on the load current, a static error, proportional to the output cur- rent, causes the output voltage to vary according to the sensed current. fig u re 9 shows the current sense circuit used to implement the load-line. the current flow- ing across the inductor dcr is read through r sg . r sg programs a trans-conductance gain and generates a current i sdroop proportional to the current delivered by the single-phase section that is then sourced from the sfb pin with proper gain eventually adjusted by the pmbus commands. r sfb gives the final gain to program the desired load-line slope ( fig u re 8 ). the output characteristic vs. load current is then given by: equation 8 where r sll is the resulting load-line resistance implemented by the single-phase section. the r sfb resistor can be then designed according to r sll as follows: equation 9 6.8 dynamic vid transition support the l6759d manages dynamic vid transitions that allow the output voltage of both sections to modify during normal device operation for power management purposes. ov, uv, and per-phase oc signals are masked during every dvid transition and they are re-activated with proper delay to prevent false triggering. total oc is active even during dvid. i scsn dcr r sg ------------ - i sout ? i sdroop == v sout vid r sfb i sdroop = vid r sfb dcr r sg ------------- i sout vid r sll i sout ? ? = ?? ? = ? ? = r sfb r sll r sg dcr ------------- ? = output voltage positioning l6759d 26/51 doc id 023240 rev 1 when dynamically changing the regulated voltage (dvid), the system needs to charge or discharge the output capacitor accordingly. this means that an extra-current i dvid needs to be delivered (especially when increasing the output regulated voltage) and it must be con- sidered when setting the overcurrent threshold of both the sections. this current results: equation 10 where dv out / dt vid depends on the specific command issued (10 mv/ sec. for setvid_fast and 2.5 mv/ sec. for setvid_slow). surpassing the total oc threshold during the dynamic vid causes the device to latch and disable. set proper filtering on i lim to pre- vent from false total-oc tripping. as soon as the controller receives a new valid command to set the vid level for one (or both) of the two sections, the reference of the involved section steps up or down according to the target vid with the programmed slope until the new code is reached. if a new valid command is issued during the transition, the device updates the target-vid level and performs the dynamic transition up to the new code. ov and uv are masked during the transition and re-activated with proper delay after the end of the transition to prevent false triggering. 6.9 dvid optimization: ref a high slew-rate for dynamic vid transitions cause overshoot and undershoot on the regulated voltage, causing a violation in the microprocessor requirement. to compensate for this behavior and to remove any undershoot in the transition, each section features a dvid optimization circuit. the reference used for the regulation is available on the ref/sref pin (see fig u re 10 ). connect an r ref /c ref to gnd to optimize the dvid behavior. the components may be designed as follows: equation 11 where ? vosc is the pwm ramp and k v the gain for the voltage loop (see s ection 11 ). during a dvid transition, the ref pin moves according to the command issued (setvidfast, setvidslow); the current requested to charge/discharge the r ref /c ref network is mirrored and added to the droop current compensating for undershoot on the regulated voltage. optimization through the ref pin is active only for downward vid transition. i dvid c out dv out dt vid ----------------- - ? = c ref c f 1 ? v osc k v v in ? ---------------------- ? ?? ?? ? = r ref r f c f ? c ref --------------------- - = l6759d output voltage positioning doc id 023240 rev 1 27/51 figure 10. dvid optimization circuit ref ref r ref c ref ref fb comp vsen r f c f r fb z f (s) z fb (s) i droop v comp fbr to vddcor e (remote sense) rgnd ref. from dac output voltage monitoring and protection l6759d 28/51 doc id 023240 rev 1 7 output voltage monitoring and protection the l6759d monitors the regulated voltage of both sections through pin vsen and svsen in order to manage ov and uv. the device shows different thresholds when in different operative conditions but the behavior in response to a protection event is still the same as described below. protection is active also during soft-start while it is properly masked during dvid transitions with an additional delay to avoid false triggering. table 8. l6759d protection at a glance 7.1 overvoltage when the voltage sensed by vsen and/or svsen overcomes the ov threshold, the control- ler acts in order to protect the load from excessive voltage levels, avoiding any possible undershoot. to reach this target, a special sequence is performed as per the following list: the reference performs a dvid transition down to 250 mv on the section which triggered the ov protection the pwm of the section which triggered the protection are switched between hiz and zero (endrv is kept high) in order to follow the voltage imposed by the dvid on-going. this limits the output voltage excursion, protects the load and assures no undershoot is generated (if vout < 250 mv, the section is hiz) the pwm of the non-involved section is set permanently to hiz (endrv is kept low) in order to realize a hiz condition osc/ flt pin is driven high power supply or en pin cycling is required to restart operations if the cause of the failure is removed, the converter ends the transition with all pwms in hiz state and the output voltage of the section which triggered the protection lower than 250 mv. 7.2 overcurrent the overcurrent threshold must be programmed to a safe value, in order to be sure that each section doesn't enter oc during normal operation of the device. this value must take section multi-phase single-phase overvoltage (ov) vsen, svsen = +150 mv above reference. action: ic latch; ls=on & pwmx = 0 (if applicable); other section: hiz. undervoltage (uv) vsen, svsen = 400 mv below reference. active after ref > 500 mv action: ic latch; both sections hiz. overcurrent (oc) current monitor across inductor dcr. dual protection, per-phase and average. action: uv-like dynamic vid protection masked with additional delay to prevent from false triggering. n/a l6759d output voltage monitoring and protection doc id 023240 rev 1 29/51 into consideration also the extra current needed during the dvid transition (i dvid ) and the process spread and temperature variations of the sensing elements (inductor dcr). moreover, since also the internal threshold spreads, the design must consider the mini- mum/maximum values of the threshold. 7.2.1 multi-phase section the l6759d features two independent load indicator signals, imon and i lim , to properly manage oc protection, current monitoring and dpm. both imon and i lim sources a current proportional to the current delivered by the regulator, as follows: equation 12 the i mon and i lim pins are connected to gnd through a resistor (r imon and r ilim respec- tively), implementing a load indicator with different targets. imon is used for current reporting purposes and for the dpm phase shedding. r imon must be designed considering that i max must correspond to 1.24 v (for correct imax detection) i lim is used for the overcurrent protection only. r ilim must be designed considering that the oc protection is triggered when v( i lim )= 2.5 v. in addition, the l6759d also performs per-phase oc protection. per-phase oc. maximum information current per-phase (i infox ) is internally limited to 35 a. this end-of-scale current (i oc_th ) is compared with the information current generated for each phase (i infox ). if the current information for the single-phase exceeds the end-of-scale current (i.e. if i infox > i oc_th ), the device turns on the ls mosfet until the threshold is re-crossed (i.e. until i infox < i oc_th ) total current oc. the i lim pin allows a maximum total output current to be defined for the system (i oc_tot ). the i lim current is sourced from the i lim pin. by connecting a resistor r ilim to gnd, a load indicator with 2.5 v (v oc_tot ) end-of-scale can be implemented. when the voltage present at the i lim pin crosses v oc_tot , the device detects an oc and immediately latches with all the mosfets of all the sections off (hiz). the typical design considers the intervention of the total current oc before the per-phase oc, leaving this last one as an extreme-protection in case of hardware failures in the exter- nal components. per-phase oc depends on the r g design while total oc is dependant on the i lim design and on the application tdc and max. current supported. the typical design flow is the following: define the maximum total output current (i oc_tot ) according to system requirements (i max , i tdc ). considering the i mon design, i max must correspond to 1.24 v (for correct imax detection) while in the i lim design, i oc_tot must correspond to 2.5 v design the per-phase oc and r g resistor in order to have i infox = i oc_th (35 a) when i out is about 10% higher than the i oc_tot current. it results: i mon i lim dcr r g ------------- i out ? == output voltage monitoring and protection l6759d 30/51 doc id 023240 rev 1 equation 13 where n is the number of phases and dcr the dc resistance of the inductors. r g should be designed in worst-case conditions design the r imon in order to have the imon pin voltage to 1.24 v at the i max current specified by the design. it results: equation 14 where i max is max. current requested by the processor (see intel documentation for details) design the r ilim in order to have the i lim pin voltage to 2.5 v at the i oc_tot current specified above. it results: equation 15 where i oc_tot is the overcurrent switch-over threshold previously defined adjust the defined values according to the bench-test of the application c ilim in parallel to r ilim can be added with a proper time constant to prevent false oc tripping and/or delay c imon in parallel to r imon can be added to adjust the averaging interval for the current reporting and/or to adjust the dpm latencies. additionally, it can be increased to prevent false total-oc tripping during dvid. note: this is the typical design flow. c u stom design and specifications may req u ire different settings and ratios between the per-phase oc threshold and the total c u rrent oc threshold. applications with big ripple across ind u ctors may be req u ired to set per-phase oc to val u es different than 110%: the design flow sho u ld be modified accordingly. 7.2.2 overcurrent and power states when the controller receives the setps command through the svi interface, it automatically changes the number of working phases. in particular, the maximum number of phases in which l6759d may work in > ps00h is limited to 2, regardless of the number n configured in ps00h. the oc level is then scaled as the controller enters > ps00h, as per ta bl e 9 . r g 1.1 i oc_tot ? () dcr ? ni ? octh ------------------------------------------------------------- - = r imon 1.24v r g ? i max dcr ? --------------------------------- = r ilim 2.5v r g ? i oc_tot dcr ? ----------------------------------------- = table 9. multi-phase section oc scaling and power states power state [hex] n oc level (v oc_tot ) 00h 2 to 3 2.500 v l6759d output voltage monitoring and protection doc id 023240 rev 1 31/51 7.2.3 single-phase section the l6759d monitors both the per-phase currents and allows the setting of an oc threshold as follows: per-phase oc. maximum information current per-phase (i sinfox ) is internally limited to 35 a. this end-of-scale current (i soc_th ) is compared with the information current generated for each phase (i sinfox ). if the current information for the single-phase exceeds the end-of-scale current (i.e. if i sinfox > i soc_th ), the device turns on the ls mosfet until the threshold is re-crossed (i.e. until i sinfox < i soc_th ). typical design is dependant on the application tdc and max. current supported. the typical design flow is the following: ? define the maximum total output current (i soc_tot ) according to system requirements (i smax , i stdc ). ? design the per-phase oc and r sg resistor in order to have i sinfox = i soc_th (35 a) when i sout = i soc_tot current. it results: equation 16 where dcr is the dc resistance of the inductors. r sg should be designed in worst- case conditions. ? adjust the defined values according to the bench-test of the application. 01h, 02h 3 1.650 v 2 2.500 v table 9. multi-phase section oc scaling and power states (continued) power state [hex] n oc level (v oc_tot ) r sg i soc_tot dcr ? i socth -------------------------------------------- - = single ntc thermal monitor and compensation l6759d 32/51 doc id 023240 rev 1 8 single ntc thermal monitor and compensation the l6759d features single ntc for thermal sensing for both thermal monitoring and compensation. thermal monitoring consists of monitoring the converter temperature eventually reporting an alarm by asserting the vr_hot signal. this is the base for the temperature zone register fill. thermal compensation consists of compensating the inductor dcr derating with temperature, so preventing drifts in any variable correlated to the dcr: voltage positioning, overcurrent, imon, current reporting. both functions share the same thermal sensor (ntc) to optimize the overall application cost without compromising performance. 8.1 thermal monitor and vr_hot the diagram for the thermal monitor is reported in fig u re 11 . ntc should be placed close to the power stage hot-spot in order to sense the regulator temperature. as the temperature of the power stage increases, the ntc resistive value decreases, so reducing the voltage observable at the tm pin. the recommended ntc is nths0805n02n6801he for accurate temperature sensing and thermal compensation. different ntc may be used: to reach the requested accuracy in temperature reporting, a proper resistive network must be used in order to match the resulting characteristic with the one coming from the recommended ntc. the voltage observed at the tm pin is internally converted and then used to fill in the temperature zone register. when the temperature observed exceeds tmax (programmed via pmbus, the default value is 110 c), the l6759d asserts vr_hot (active low - as long as the overtemperature event lasts) and the alert# line (until reset by the getreg command on the status register). figure 11. thermal monitor connections vcc5 tm temperature decoding vr_hot temp. zone 2k ntc l6759d single ntc thermal monitor and compensation doc id 023240 rev 1 33/51 8.2 thermal compensation the l6759d supports dcr sensing for output voltage positioning: the same current information used for voltage positioning is used to define the overcurrent protection and the current reporting (register 15h in svi). having imprecise and temperature-dependant information leads to a violation of the specifications and misleading information returned to the svi master: a positive thermal coefficient specific to dcr needs to be compensated to get stable behavior of the converter as the temperature increase. un-compensated systems show temperature dependencies on the regulated voltage, overcurrent protection and current reporting (reg 15h). the temperature information available on the tm pin and used for the thermal monitor may be used also for this purpose. by comparing the voltage on the tm pin with the voltage present on the tcomp pin, the l6759d gives a correction to the i droop current used for voltage positioning (see s ection 6.3 ) therefore recovering the dcr temperature deviation. depending on ntc location and distance from the inductors and the available airflow, the correlation between ntc temperature and dcr temperature may be different: tcomp adjustments allow modification of the gain between the sensed temperature and the correction made upon the i droop current. short tcomp to gnd to disable thermal compensation (no correction is given to i droop ). 8.3 tm and tcomp design this procedure applies to both single-phase and multi-phase sections. 1. properly choose the resistive network to be connected to the tm pin. the recommended values/network is reported in fig u re 11 2. connect the voltage generator to the tcomp pin (default value 3.3 v) 3. power on the converter and load the thermal design current (tdc) with the desired cooling conditions. record the output voltage regulated as soon as the load is applied 4. wait for thermal steady-state. adjust down the voltage generator on the tcomp pin in order to get the same output voltage recorded at point #3 5. design the voltage divider connected to tcomp (between vcc5 and gnd) in order to get the same voltage set to tcomp at point #4 6. repeat the test with the tcomp divider designed at point #5 and verify the thermal drift is acceptable. in case of positive drift (i.e. output voltage at thermal steady-state is bigger than the output voltage immediately after loading tdc current), change the divider at the tcomp pin in order to reduce the tcomp voltage. in case of negative drift (i.e. output voltage at thermal steady-state is smaller than the output voltage immediately after loading tdc current) change the divider at the tcomp pin in order to increase the tcomp voltage 7. the same procedure can be implemented with a variable resistor in place of one of the resistors of the divider. in this case, once the compensated configuration is found, simply replace the variable resistor with a resistor with the same value. efficiency optimization l6759d 34/51 doc id 023240 rev 1 9 efficiency optimization as per vr12 specifications, the svi master may define different power states for the vr controller. this is performed by setps commands. the l6759d re-configures itself to improve overall system efficiency according to ta bl e 1 0 . 9.1 dynamic phase management (dpm) dynamic phase management allows the number of working phases to be adjusted according to the delivered current still maintaining the benefits of the multi-phase regulation. the phase number is reduced by monitoring the voltage level across the imon pin: the l6759d reduces the number of working phases according to the strategy defined by the pin- strapping configured and/or pmbus(tm) commands received (see ta b l e 6 ). dpm12 refers to the current at which the controller changes from 1 to 2 phases while dpm23 defines the current at which the controller changes from 2 to 3 phases. when dpm is enabled, the l6759d starts monitoring the imon voltage for phase number modification after vr_rdy has transition high: the soft-start is then implemented in interleaving mode with all the available phases enabled. dpm is reset in case of a setvid command that affects the multi-phase section and when ltb technology ? detects a load transient. after being reset, if the voltage across imon is compatible, dpm is re-enabled after a proper delay. delay in the intervention of dpm can be adjusted by properly sizing the filer across the imon pin. increasing the capacitance results in increased delay in the dpm intervention. note: d u ring load transients with light slope, the filtering of imon may res u lt too slow for the ic to set the correct n u mber of phases req u ired for the c u rrent effectively loading the system (ltb does not trigger in case of light slopes). the l6759d feat u res a safety mechanism which re- enables phases that were switched off by comparing i lim and imon pin voltage. in fact, the i lim pin is lightly filtered in order to perform a fast reaction of oc protection while imon is heavily filtered to perform the correct averaging of the information. while working contin u o u sly in dpm, the device compares the information of imon and i lim : i lim voltage is divided into n steps with a width of v ocp /(2*n) (where v ocp = 2.5 v and n the n u mber of st u ffed phases). if the dpm phase n u mber res u lting from imon is not coherent with the step in which i lim stays, the phase n u mber is increased accordingly.the mechanism is active only to increase the phase n u mber which is red u ced again by dpm. table 10. efficiency optimization feature ps00h ps01h dpm according to pin-strapping and pmbus(tm). active. 1phase/2phase according to iout. vfde active when in single-phase and dpm enabled. active when in single-phase gdc according to pin-strapping and pmbus(tm). gdc set to 5 v. l6759d efficiency optimization doc id 023240 rev 1 35/51 9.2 variable frequency diode emulation (vfde) as the current required by the load is reduced, the l6759d progressively reduces the number of switching phases according to dpm settings on the multi-phase section. if single- phase operation is configured, when the delivered current approaches the ccm/dcm boundary, the controller enters vfde operation. the single-phase section, being a single- phase, enters vfde operation always when the delivered current approaches the ccm/dcm boundary. in a common single-phase dc-dc converter, the boundary between ccm and dcm is when the delivered current is perfectly equal to 1/2 of the peak-to-peak ripple into the inductor (iout = ipp/2). further decreasing the load in this condition maintaining ccm operation would cause the current into the inductor to reverse, therefore sinking current from the output for a part of the off-time. this results in poor system efficiency. the l6759d is able (via cspx/csnx pins) to detect the sign of the current across the +inductor (zero cross detection, zcd), so it is able to recognize when the delivered current approaches the ccm/dcm boundary. in vfde operation, the controller fires the high-side mosfet for a ton and the low-side mosfet for a toff (the same as when the controller works in ccm mode) and waits for the necessary time until the next firing in high-impedance (hiz). the consequence of this behavior is a linear reduction of the ?apparent? switching frequency that, in turn, results in an improvement of the efficiency of the converter when in very light load conditions. to prevent entering the audible range, the ?apparent? switching frequency reduction is limited to 30 khz. 9.3 gate drive control (gdc) gate drive control (gdc) is a proprietary function which allows the l6759d to dynamically control the power mosfets driving voltage in order to further optimize the overall system efficiency. according to the svi power state commanded and the configuration received through the pmbus, the device switches this pin (gdc) between the vcc5 or vdrv (inputs). by connecting the power supply of external drivers directly to this pin, it is then possible to control carefully the external mosfet driving voltage. figure 12. output current vs. switching frequency in psk mode t io u t = ipp/2 t io u t < ipp/2 t s w t s w tvfde efficiency optimization l6759d 36/51 doc id 023240 rev 1 in fact, high driving voltages are required to get good efficiencies in high loading conditions. on the contrary, in lower loading conditions, such high driving voltage penalizes efficiency because of high losses in qgs. gdc allows to tune the mosfet driving voltage according to the delivered current. default configuration considers gdc always switched to vdrv except when the current monitor is lower than n*10 or when entering power states higher than ps01h (included): in this case, to further increase efficiency, simply supply the phase1 and phase2 driver through the gdc pin. their driving voltage is automatically updated as lower power states are commanded through the svi interface. further optimization may be possible by properly setting the automatic gdc threshold through a dedicated pmbus command. it is then possible to modify the gate driving voltage switch-over in ps00h. according to the positioning of the threshold compared with dpm thresholds, it is possible to achieve different performances. simulations and/or bench tests may be of help in defining the best performing configuration achievable with the active and passive components available. fig u re 13 gives a comparison of the efficiency improvements with dpm/gdc enabled with respect to standard solutions. figure 13. efficiency performances with and without enhancements (dpm, gdc) l6759d main oscillator doc id 023240 rev 1 37/51 10 main oscillator the internal oscillator generates the triangular waveform for the pwm charging and discharging an internal capacitor with a constant current. the switching frequency for each channel is internally fixed at 200 khz (f sw ) and at 230 khz (f ssw ): the resulting switching frequency at the load side for the multi-phase section results in being multiplied by n (number of configured phases). the current delivered to the oscillator is typically 20 a and may be varied using an external resistor (r osc , r sosc ) typically connected between the osc, sosc pins and gnd. since the osc/sosc pins are fixed at 1.02 v, the frequency is varied proportionally to the current sunk from the pin considering the internal gain of 10 khz/ a for the multi-phase section and of 11.5 khz/ a for the single-phase section, see fig u re 14 . by connecting r osc /r sosc to sgnd the frequency is increased (current is sunk from the pin), according to the following relationships: equation 17 equation 18 connecting r osc /r sosc to a positive voltage vbias, the frequency is reduced (current is injected into the pin), according to the following relationships: equation 19 equation 20 f sw 200khz 1.02v r osc k ? () --------------------------- 10 khz a ---------- - ? + = f ssw 230khz 1.02v r sosc k ? () ------------------------------ - 11.5 khz a ---------- - ? + = f sw 200khz vbias 1.02v ? r osc k ? () ------------------------------------- - 10 khz a ---------- - ? ? = f ssw 230khz vbias 1.02v ? r sosc k ? () -------------------------------------- 11.5 khz a ---------- - ? ? = main oscillator l6759d 38/51 doc id 023240 rev 1 figure 14. r osc vs. f sw per phase (r osc to gnd - left; r osc to 3.3v - right) 10.1 lsless startup and pre-bias output any time the device resumes from an ?off? code and at the first power-up, in order to avoid any kind of negative undershoot on the load side, the l6759d performs a special sequence in enabling the drivers: during the soft-start phase, the ls driver results as disabled (ls=off - pwmx set to hiz and endrv = 0) until the first pwm pulse. after the first pwm pulse, pwmx outputs switch between logic ?0? and logic ?1? and endrv is set to logic ?1?. this particular sequence avoids a dangerous negative spike on the output voltage that can happen if starting over a pre-biased output. low-side mosfet turn-on is masked only from the control loop point of view: protections are still allowed to turn on the low-side mosfet in the case of overvoltage if needed. figure 15. lsless startup: enabled (left) and disabled (right) do?]r wz? ^ ?]}v ^]vpo r wz? ^ ?]}v do?]r wz? ^ ?]}v ^]vpo r wz? ^ ?]}v l6759d system control loop compensation doc id 023240 rev 1 39/51 11 system control loop compensation the control system can be modeled with an equivalent single-phase converter whose only difference is the equivalent inductor l/n (where each phase has an l inductor and n is the number of the configured phases), see fig u re 16 . figure 16. equivalent control loop the control loop gain results (obtained opening the loop after the comp pin): equation 21 where: r ll is the equivalent output resistance determined by the droop function (voltage positioning) z p (s) is the impedance resulting from the parallel of the output capacitor (and its esr) and the applied load r o z f (s) is the compensation network impedance z l (s) is the equivalent inductor impedance a(s) is the error amplifier gain is the pwm transfer function. the control loop gain is designed in order to obtain a high dc gain to minimize static error and to cross the 0db axes with a constant -20 db/dec slope with the desired crossover frequency t . neglecting the effect of z f (s), the transfer function has one zero and two poles; both the poles are fixed once the output filter is designed (lc filter resonance lc ) and the zero ( esr ) is fixed by esr and the droop resistance. ref fb comp vsen r f c f r fb pwm l/n esr c o r o d v comp v out z f (s) z fb (s) i droop v comp fbr rgnd g loop s () pwm z f s () r ll z p s () + () ?? z p s () z l s () + [] z f s () as () -------------- 1 1 as () ----------- - + ?? ?? r fb ? + ? ------------------------------------------------------------------------------------------------------------------------ - ? = pwm 9 10 ------ v in ? v osc ------------------ - ? = system control loop compensation l6759d 40/51 doc id 023240 rev 1 figure 17. control loop bode diagram and fine tuning to obtain the desired shape, an r f -c f series network is considered for the z f (s) implementation. a zero at f =1/r f c f is then introduced together with an integrator. this integrator minimizes the static error while placing the zero f in correspondence with the l- c resonance which assures a simple -20 db/dec shape of the gain. in fact, considering the usual value for the output filter, the lc resonance results to be at a frequency lower than the above reported zero. the compensation network can be designed as follows: equation 22 equation 23 11.1 compensation network guidelines the compensation network design assures the presence of a system response according to the crossover frequency selected and to the output filter considered: it is anyway possible to further fine-tune the compensation network modifying the bandwidth in order to get the best response of the system, as follows (see fig u re 17 ): increase r f to increase the system bandwidth accordingly decrease r f to decrease the system bandwidth accordingly increase c f to move f to low frequencies increasing as a consequence the system phase margin. having the fastest compensation network does not guarantee that the load requirements are satisfied: the inductor still limits the maximum di/dt that the system can afford. in fact, when a load transient is applied, the best that the controller can do is to ?saturate? the duty cycle to its maximum (d max ) or minimum (0) value. the output voltage dv/dt is then limited by the inductor charge / discharge time and by the output capacitance. in particular, the most db z f (s) g loop (s) k lc = f esr t r f [db] db z f (s) g loop (s) k lc = f esr t r f [db] r f c f r f r fb ? v osc ? v in ------------------------------------ - 10 6 ------ f sw l ? r ll esr + () --------------------------------- - ?? = c f c o l ? r f ---------------------- - = l6759d system control loop compensation doc id 023240 rev 1 41/51 limiting transition corresponds to the load-removal since the inductor results as being discharged only by v out (while it is charged by v in -v out during a load appliance). note: the introd u ction of a capacitor (c i ) in parallel to r fb significantly speeds u p the transient response by co u pling the o u tp u t voltage dv/dt on the fb pin, therefore u sing the error amplifier as a comparator. the comp pin s u ddenly reacts and, also thanks to the ltb te c h n o l o gy ? control scheme, all the phases can be t u rned on together to immediately give to the o u tp u t the req u ired energy. typical design considers starting from val u es in the range of 100 pf validating the effect by bench testing. an additional series resistor (r i ) can also be u sed. 11.2 ltb technology ltb technology further enhances the performance of the controller by reducing the system latencies and immediately turning on all the phases to provide the correct amount of energy to the load optimizing the output capacitor count. ltb technology monitors the output voltage through a dedicated pin detecting load- transients with selected dv/dt, it cancels the interleaved phase-shift, simultaneously turning on all phases. the ltb detector is able to detect output load transients by coupling the output voltage through an r lt b - c ltb network. after detecting a load transient, all the phases are turned on together and the ea latencies results as bypassed as well. sensitivity of the load transient detector can be programmed in order to control precisely both the undershoot and the ring-back. ltb technology design tips. decrease r lt b to increase the system sensitivity making the system sensitive to smaller dv out increase c ltb to increase the system sensitivity making the system sensitive to higher dv/dt increase r i to increase the width of the ltb pulse increase c i to increase the ltb sensitivity over frequency. pmbus support l6759d 42/51 doc id 023240 rev 1 12 pmbus support the l6759d is compatible with pmbus ? standard revision 1.1, refer to pmbus standard documentation for further information (www.pmbus.org). table 11. supported commands command per rail code [hex] mode comments operation y 01 rw byte used to turn the controller on/off in conjunction with the input from the control pin. also used to set margin voltages. soft-off not supported on_off_config n 1 02 rw byte configures how the controller responds when power is applied. write_protect y 10 rw byte controls writing to the pmbus device to prevent accidental changes. vout_command y 21 rw word causes the converter to set it's output voltage to the commanded value - vid mode. vout_max y 24 rw word sets the upper limit on the output voltage regardless of any other command vout_margin_high y 25 rw word sets the voltage to which the output is to be changed when the operation command is set to ?margin high? vout_margin_low y 26 rw word sets the voltage to which the output is to be changed when the operation command is set to ?margin low? iout_cal_offset y 39 rw word calibration for iout reading. ot_fault_limit y 4f rw word overtemperature fault threshold. ot_warn_limit y 51 rw word overtemperature warning threshold. vin_ov_fault_limit n 55 rw word input voltage monitor overvoltage limit. vin_uv_fault_limit n 59 rw word input voltage monitor undervoltage limit. mfr_specific_01 n d1 rw byte average_time_scale. sets the time between two measures. mfr_specific_02 y d2 rw byte debug_mode. [01/10] switch [on/off] the vout control on pmbus domain. mfr_specific_05 y d5 rw byte vout_trim. used to apply a fixed offset voltage to the output voltage command value. mfr_specific_08 y d8 rw byte vout_droop. used to change the vout droop. mfr_specific_35 n 1 f3 rw byte manual_phase_shedding. used to manage the phase shedding manually. mfr_specific_38 y f6 rw byte vout_ov_fault_limit allows the programming of the ov protection threshold for each rail. mfr_specific_39 y f7 rw byte vfde_enable. mfr_specific_40 y f8 rw byte ultrasonic_enable. mfr_specific_41 n 1 f9 rw byte gdc_threshold. to access the internal register to set gdc threshold [a] l6759d pmbus support doc id 023240 rev 1 43/51 mfr_specific_42 n 1 fa rw byte dpm12_threshold. to access the internal register to set the dpm12 threshold [a] mfr_specific_43 n 1 fb rw byte dpm23_threshold. to access the internal register to set the dpm23 threshold [a] capability n 19 r byte it provides a way for a host system to determine key capabilities of a pmbus device, such as maximum bus speed and pmbus alert. vout_mode n 20 r byte the device operates in vid mode. pmbus_revision n 98 r byte revision of the pmbus which the device is compliant to mfr_id n 99 r block returns the manufacturer id mfr_model n 9a r block returns manufacturer model number mfr_revision n 9b r block returns the device revision number mfr_specific_25 n e9 r byte st_model_id mfr_specific_exten ded_command_00 y 00 r byte vr12_status1 mfr_specific_exten ded_command_01 y 01 r byte vr12_status2 mfr_specific_exten ded_command_02 y 02 r byte vr12_tempzone mfr_specific_exten ded_command_03 y 03 r byte vr12_iout mfr_specific_exten ded_command_05 y 05 r byte vr12_vrtemp mfr_specific_exten ded_command_07 y 07 r byte vr12_status2_lastread mfr_specific_exten ded_command_08 y 08 r byte vr12_iccmax mfr_specific_exten ded_command_09 y 09 r byte vr12_tempmax mfr_specific_exten ded_command_10 y 0a r byte vr12_srfast mfr_specific_exten ded_command_11 y 0b r byte vr12_srslow mfr_specific_exten ded_command_12 y 0c r byte vr12_vboot mfr_specific_exten ded_command_13 y 0d r byte vr12_voutmax mfr_specific_exten ded_command_14 y 0e r byte vr12_vidsetting table 11. supported commands (continued) command per rail code [hex] mode comments pmbus support l6759d 44/51 doc id 023240 rev 1 note: 1 applies to m u lti-phase only. 2 applies to single-phase only. mfr_specific_exten ded_command_15 y 0f r byte vr12_pwrstate mfr_specific_exten ded_command_16 y 10 r byte vr12_offset clear_faults n 03 send byte used to clear any fault bits that have been set read_vin n 88 r word returns the input voltage in volts (vin pin) read_vout y 8b r word returns the actual reference used for the regulation in vid format. read_iout y 8c r word returns the output current in amps read_duty_cycle n 1 94 r word returns the duty cycle of the devices? main power converter in percentage mfr_specific_04 y d4 r word read_vout. returns the actual reference used for the regulation in volts for linear format. read_temperature_ 1 y 8d r word read_temperature. [degc] status_byte y 78 r byte one byte with information on the most critical faults. status_word y 79 r word two bytes with information on the units? fault condition. status_vout y 7a r byte status information on the output voltage warnings and faults. status_iout y 7b r byte status information on the output current warnings and faults. status_temperature y 7d r byte status information on the temperature warnings and faults. status_cml y 7e r byte status information on the units communication, logic and memory. status_input n 1 7c r byte status information on the input warning and fault status_mfr_specific y 80 r byte manufacturer specific status table 11. supported commands (continued) command per rail code [hex] mode comments l6759d pmbus support doc id 023240 rev 1 45/51 12.1 enabling the device through pmbus the default condition for the l6759d is to power up through the en pin ignoring pmbus commands. by properly setting the on_off_config command, it is also possible to let the device ignore the en pin acting only as a consequence of the operation command issued. 12.2 controlling vout through pmbus vout can be set independently from the setvid commands issued through the svi interface by using pmbus. two main modes can be identified: offset above svi commanded voltage. by enabling the margin mode through the operation command and by commanding the margin_high and margin_low registers, it is possible to dynamically control an offset above the output voltage commanded through the svi bus. fixed vout regardless of svi.it is necessary to enter debug_mode. in this condition, commands from svi are acknowledged but not executed and vout_command controls the voltage regulated on the output.the l6759d can enter and exit debug_mode anytime. upon any transition, vout remains unchanged and only the next-coming command affects the output voltage positioning (i.e. when exiting debug_mode, returning to svi domain, the output voltage remains unchanged until the next setvid command). figure 18. device initialization: pmbus controlling vout vcc5 vdrv vin uvlo 2msec por uvlo uvlo 50usec en svi bus pmbus vddq / vtt envtt (ignored by on_off_config setting) vrrdy / svrrdy 64usec on-off_config operation command rejected command ack but not executed pmbus support l6759d 46/51 doc id 023240 rev 1 12.3 input voltage monitoring (read_vin) the dedicated pmbus command allows the user to monitor input voltage. by connecting the vin pin to the input voltage with recommended resistor values, the l6759d returns the value of the input voltage measured as a voltage (linear format, n= -4). the divider needs to be programmed to have 1.24 v on the pin when vin=15.9375 v. according to this, r up =118.5 k ? and r down =10 k ? . errors in defining the divider lead to monitoring errors accordingly. filter the vin pin locally to gnd to increase stability of the voltage being measured. 12.4 duty cycle monitoring (read_duty) the dedicated pmbus command allows the user to monitor duty cycle for multi-phase with the aim of calculating input current inexpensively (no need for input current sense resistors). by connecting the phase pin to the phase1 phase pin, the l6759d returns the value of the duty-cycle as a percentage (linear format, n=-2). the divider needs to be programmed to respect absolute maximum ratings for the pin (7 vmax). according to this, r up =5.6 k ? and r down =470 ? . 12.5 output voltage monitoring (read_vout) the dedicated pmbus command allows the user to monitor the output voltage for both sections. the l6759d returns the value of the programmed vid in vid lsbs (i.e. number of lsbs. c8h = 200 dec x 5 mv = 1.000 v). 12.6 output current monitoring (read_iout) the dedicated pmbus command allows the user to monitor the output current for the multi- phase section. the l6759d returns the value of the delivered current by reading imon voltage (same as vr12 register 15h) in amperes (linear format, n=0). 12.7 temperature monitoring (read_temperature) the dedicated pmbus command allows the user to monitor the temperature of the power section for multi-phase. the l6759d returns the value of the temperature sensed by ntc connected on the tm pin (the same as vr12 temperature zone) in celsius degrees (linear format, n=0). l6759d pmbus support doc id 023240 rev 1 47/51 12.8 overvoltage threshold setting the dedicated mfr_specific command allows the programming of a specific threshold for multi-phase and single-phase sections. the threshold can be programmed according to ta b l e 1 2 . different thresholds can be configured for multi-phase and single-phase sections. this product is subject to a limited license from power-one, inc. related to digital power technology patents owned by power-one, inc. this license does not extend to stand-alone power supply products. table 12. ov threshold setting data byte [hex] oc threshold [mv] (above programmed vid) 00h +175 mv (default) 01h +225 mv 02h +275 mv 03h +325 mv package mechanical data l6759d 48/51 doc id 023240 rev 1 13 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. table 13. vfqfpn48 (6x6 mm) mechanical data dim. mm min. typ. max. a 0.80 0.90 1.00 a1 0 0.02 0.05 d6.00 d2 4.40 e6.00 e2 4.40 b 0.15 0.20 0.25 e0.40 k0.20 l 0.25 0.35 0.45 aaa 0.10 bbb 0.07 ccc 0.10 l6759d package mechanical data doc id 023240 rev 1 49/51 figure 19. vfqfpn48 (6x6 mm) package drawing ccc c plane seating 0.08 c 8 a b c bbb c a b 7 4 index area (d/2 xe/2) (d/2 xe/2) 4 index area aaa c 2x top view 9 aaa c 2x side view bottom view pin#1 id d e e nxb a1 a d2 e2 nxl nxk r0.30 13 12 25 24 48 1 37 36 revision history l6759d 50/51 doc id 023240 rev 1 14 revision history table 14. document revision history date revision changes 31-may-2012 1 initial release. l6759d doc id 023240 rev 1 51/51 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 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